In circuits produced on the basis of microtechnologies and nanotechnologies, the faults resulting from physical defects due to burning-in may cause operating errors and finally the failure of the system. One way of preventing these failures is to mask or to correct the errors. Masking can be carried out for example with the aid of a majority vote on redundant systems, while usually the correction is based on a detection method combined with mechanisms for reconfiguring and reexecuting the faulty operation. Unfortunately, masking and correction have considerable extra costs notably in hardware and in power.
The cost of the “mitigation” of the physical defects due to burning-in may be reduced significantly if it is considered that the majority of these defects show themselves through a progressive increase in the latency of the circuit. Consequently, a less costly approach is to prevent the appearance of the failures by detecting the possible delay faults due to burning-in before they generate errors. One monitoring technique that allows detection by anticipation of these faults consists in testing the systems in “degraded” mode. In the present description, the word “degraded” is defined as being a slight deterioration of the parameters of the circuit during its test, this term being known to those skilled in the art to denote an operating state. For example, the clock frequency of a synchronous circuit may be slightly increased and/or its power supply voltage slightly reduced. This offset between the operating parameters in degraded mode and in normal (nondegraded) mode provides a time margin during which the faults due to burning-in become detectable before causing errors in normal mode. This detection is equivalent to an anticipation of the errors that might appear during the operation of the circuit in normal (nondegraded) mode.
In current circuits, this type of degradation is implemented with the aid of the infrastructure which allows the management of the power supply voltage and the working frequency.
Normally, a system on a chip is divided into several voltage-frequency islands, that is to say that each island has its own hardware infrastructure for the management of its voltage and its frequency. Unfortunately, the size of these islands is relatively large and does not allow testing in degraded mode of certain portions of the circuit which, episodically, are not used, while other portions of the circuit in the same voltage-frequency island execute operative tasks. In addition, the latency with which the power supply voltage and/or the frequency can be changed is relatively low and not suited to the application of the degraded mode.